CY37064P44-125JIT
| Do pobrania | Download |
|---|---|
| Main description | CPLD Ultra37000 Family 2K Gates 64 Macro Cells 125MHz 5V 44-Pin PLCC T/R |
CPLD Ultra37000 Family 2K Gates 64 Macro Cells 125MHz 5V 44-Pin PLCC T/R
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSNo (2011/65/EU)
- Automotive No
Informacje dodatkowe
- Crosses 344
- PCNs 26
- FoundINBOMs 1
- MaskPart CY37064P44125JI%
- IntroductionDate Jul 07, 2003
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY37064P44-125JIT
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 2000
- Family Name Ultra37000
- I/O Voltage (V) 3.3|5
- In-System Programmability Yes
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 6.5
- Maximum Internal Frequency (MHz) 125
- Maximum Propagation Delay Time (ns) 10
- Memory Size (Kbit) N/R
- Number of Flip Flops N/A
- Number of Global Clocks 4
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers N/A
- Number of Logic Blocks/Elements 4
- Number of Macro Cells 64
- Number of Product Terms per Macro 16
- Number of User I/Os 37
- Process Technology N/A
- Program Memory Type ROMLess
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support Yes
- Speed Grade 125
- Supplier Temperature Grade Industrial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) 5
- Tradename Ultra37000