CY37256VP160-100AXI
| Do pobrania | Download |
|---|---|
| Main description | CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 100MHz 3.3V 160-Pin TQFP Tray |
CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 100MHz 3.3V 160-Pin TQFP Tray
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSYes (2011/65/EU, 2015/863)
- Automotive No
Informacje dodatkowe
- Crosses 143
- PCNs 27
- FoundINBOMs 1
- MaskPart CY37256VP160100AXI%
- IntroductionDate Jul 07, 2003
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY37256VP160-100AXI
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 7700
- Family Name Ultra37000
- I/O Voltage (V) 3.3|5
- In-System Programmability Yes
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 6.5
- Maximum Internal Frequency (MHz) 100
- Maximum Propagation Delay Time (ns) 12
- Memory Size (Kbit) N/R
- Number of Flip Flops N/A
- Number of Global Clocks 4
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers N/A
- Number of Logic Blocks/Elements 16
- Number of Macro Cells 256
- Number of Product Terms per Macro 16
- Number of User I/Os 133
- Process Technology N/A
- Program Memory Type ROMLess
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support Yes
- Speed Grade 100
- Supplier Temperature Grade Industrial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) 5
- Tradename Ultra37000