CY37512VP400-66BBC
| Do pobrania | Download |
|---|---|
| Main description | CPLD Ultra37000 Family 15K Gates 512 Macro Cells 66MHz 3.3V 400-Pin FBGA |
CPLD Ultra37000 Family 15K Gates 512 Macro Cells 66MHz 3.3V 400-Pin FBGA
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSNo (2011/65/EU)
- Automotive No
Informacje dodatkowe
- Crosses 6
- PCNs 27
- FoundINBOMs 1
- MaskPart CY37512VP40066BBC%
- IntroductionDate Aug 02, 2000
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY37512VP400-66BBC
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 15000
- Family Name Ultra37000
- I/O Voltage (V) 3.3|5
- In-System Programmability Yes
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 10
- Maximum Internal Frequency (MHz) 66
- Maximum Propagation Delay Time (ns) 20
- Memory Size (Kbit) N/A
- Number of Flip Flops N/A
- Number of Global Clocks 4
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers N/A
- Number of Logic Blocks/Elements 32
- Number of Macro Cells 512
- Number of Product Terms per Macro 16
- Number of User I/Os 269
- Process Technology N/A
- Program Memory Type EEPROM
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support Yes
- Speed Grade 66
- Supplier Temperature Grade Commercial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) 5
- Tradename Ultra37000