CY39200Z208-125NC
| Do pobrania | Download |
|---|---|
| Main description | CPLD Delta39K Family 200K Gates 3072 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP |
CPLD Delta39K Family 200K Gates 3072 Macro Cells 125MHz 0.18um Technology 1.8V 208-Pin PQFP
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSNo (2011/65/EU)
- Automotive No
Informacje dodatkowe
- Crosses 4
- PCNs 24
- FoundINBOMs 1
- MaskPart CY39200Z208125NC%
- IntroductionDate Dec 10, 2002
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY39200Z208-125NC
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 200000
- Family Name Delta39K
- I/O Voltage (V) 1.5|1.8|2.5|3.3
- In-System Programmability Yes
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 7
- Maximum Internal Frequency (MHz) N/A
- Maximum Propagation Delay Time (ns) 10
- Memory Size (Kbit) N/R
- Number of Flip Flops N/A
- Number of Global Clocks 4
- Number of I/O Banks 8
- Number of Inter Dielectric Layers 6
- Number of Logic Blocks/Elements N/A
- Number of Macro Cells 3072
- Number of Product Terms per Macro 16
- Number of User I/Os 136
- Process Technology 0.18um
- Program Memory Type ROMLess
- Programmability Yes
- RAM Bits (Kbit) 480
- Reprogrammability Support Yes
- Speed Grade 125
- Supplier Temperature Grade Commercial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) 3.3
- Tradename Delta39K