CY7C335-66WC
| Do pobrania | Download |
|---|---|
| Main description | CPLD CY7C330 Family 12 Macro Cells 5V 28-Pin Windowed CDIP |
CPLD CY7C330 Family 12 Macro Cells 5V 28-Pin Windowed CDIP
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSNo (2011/65/EU)
- Automotive No
Informacje dodatkowe
- Crosses 12
- PCNs 24
- FoundINBOMs 1
- MaskPart CY7C33566WC%
- IntroductionDate Jan 23, 1996
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY7C335-66WC
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates N/A
- Family Name CY7C330
- I/O Voltage (V) N/A
- In-System Programmability No
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) N/A
- Maximum Internal Frequency (MHz) N/A
- Maximum Propagation Delay Time (ns) 20
- Maximum Storage Temperature (°C) 150
- Memory Size (Kbit) N/R
- Minimum Storage Temperature (°C) -65
- Number of Flip Flops N/A
- Number of Global Clocks N/A
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers N/A
- Number of Logic Blocks/Elements N/A
- Number of Macro Cells 12
- Number of Product Terms per Macro 32
- Number of User I/Os 12
- Process Technology N/A
- Program Memory Type ROMLess
- Programmability No
- RAM Bits (Kbit) N/A
- Reprogrammability Support Yes
- Speed Grade 66
- Supplier Temperature Grade Commercial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) N/A