CY7C341B-25JXC
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|---|---|
| Main description | CPLD MAX® Family 3.75K Gates 192 Macro Cells 50MHz 0.65um, CMOS Technology 5V 84-Pin PLCC |
CPLD MAX® Family 3.75K Gates 192 Macro Cells 50MHz 0.65um, CMOS Technology 5V 84-Pin PLCC
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSYes (2011/65/EU, 2015/863)
- Automotive No
Informacje dodatkowe
- Crosses 1
- PCNs 24
- FoundINBOMs 2
- MaskPart CY7C341B25JXC%
- IntroductionDate Jul 25, 2000
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY7C341B-25JXC
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 3750
- Family Name MAX®
- I/O Voltage (V) N/A
- In-System Programmability No
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 14
- Maximum Internal Frequency (MHz) 62.5
- Maximum Propagation Delay Time (ns) 25
- Memory Size (Kbit) N/A
- Number of Flip Flops 192
- Number of Global Clocks N/A
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers 2
- Number of Logic Blocks/Elements 12
- Number of Macro Cells 192
- Number of Product Terms per Macro N/A
- Number of User I/Os 64
- Process Technology 0.65um, CMOS
- Program Memory Type EPROM
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support No
- Speed Grade 25
- Supplier Temperature Grade Commercial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) N/A
- Tradename MAX