CY7C344B-20WI
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|---|---|
| Main description | CPLD MAX® Family 600 Gates 32 Macro Cells 62.5MHz 0.65um, CMOS Technology 5V 28-Pin Windowed CDIP |
CPLD MAX® Family 600 Gates 32 Macro Cells 62.5MHz 0.65um, CMOS Technology 5V 28-Pin Windowed CDIP
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSNo (2011/65/EU)
- Automotive No
Informacje dodatkowe
- Crosses 4
- PCNs 24
- FoundINBOMs 1
- MaskPart CY7C344B20WI%
- IntroductionDate Aug 07, 1996
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY7C344B-20WI
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 600
- Family Name MAX®
- I/O Voltage (V) N/A
- In-System Programmability No
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 12
- Maximum Internal Frequency (MHz) 71.4
- Maximum Propagation Delay Time (ns) 20
- Memory Size (Kbit) N/A
- Number of Flip Flops 32
- Number of Global Clocks N/A
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers 2
- Number of Logic Blocks/Elements 1
- Number of Macro Cells 32
- Number of Product Terms per Macro N/A
- Number of User I/Os 16
- Process Technology 0.65um, CMOS
- Program Memory Type EPROM
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support No
- Speed Grade 20
- Supplier Temperature Grade Industrial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) N/A
- Tradename MAX