CY7C346-25HXC
| Do pobrania | Download |
|---|---|
| Main description | CPLD MAX® Family 2.5K Gates 128 Macro Cells 0.8um Technology 5V 84-Pin Windowed LCC |
CPLD MAX® Family 2.5K Gates 128 Macro Cells 0.8um Technology 5V 84-Pin Windowed LCC
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSYes (2011/65/EU)
- Automotive No
Informacje dodatkowe
- Crosses 2
- PCNs 24
- FoundINBOMs 2
- MaskPart CY7C34625HXC%
- IntroductionDate Jul 25, 2000
- EnablingEnergyEfficiency No
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY7C346-25HXC
Parametry
- Clock Management N/A
- Data Gate No
- Device Logic Cells N/A
- Device System Gates 2500
- Family Name MAX®
- I/O Voltage (V) N/A
- In-System Programmability No
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) N/A
- Maximum Internal Frequency (MHz) N/A
- Maximum Propagation Delay Time (ns) N/A
- Memory Size (Kbit) N/A
- Number of Flip Flops 128
- Number of Global Clocks N/A
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers 2
- Number of Logic Blocks/Elements N/A
- Number of Macro Cells 128
- Number of Product Terms per Macro N/A
- Number of User I/Os 64
- Process Technology 0.8um
- Program Memory Type EPROM
- Programmability Yes
- RAM Bits (Kbit) N/A
- Reprogrammability Support No
- Speed Grade 25
- Supplier Temperature Grade Commercial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) N/A
- Tradename MAX